Z80182 Datasheet, PDF (83/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
TIMING DIAGRAMS
Z180 MPU Timing
Opcode Fetch Cycle
I/O Write Cycle †
I/O Read Cycle †
T1
T2
TW
T3
T1
T2
TW
T3
5
4
2
3
ø
Address
/WAIT
1
6
20
20
19
19
11
7
12
/MREQ
/IORQ
/RD
/WR
/M1
8
9
10
14
18
7
29
11
13
28
13
9
22
25
26 and 26a
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
T1
11
11
ST
Data
IN
Data
OUT
62
/RESET
68
17
63
67
15
16
23
15
24
62
67
16
21
27
63
68
Figure 90. CPU Timing
(Opcode Fetch Cycle, Memory Read/Write Cycle
I/O Read/Write Cycle)
DS971820600
3-83