Z80182 Datasheet, PDF (69/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
16550 MIMIC REGISTERS
The Z80182/Z8L182 contains the following set of registers
for interfacing with the PC/XT/AT.
– Receive Buffer Register
– Transmit Holding Register
– Interrupt Enable Register
– Interrupt Identification Register
– FIFO Control Register
– Line Control Register
– Modem Control Register
– Line Status Register
– Modem Status Register
– Scratch Register
– Divisor Latch Least/Most Significant Bytes
– FIFO Control Register
These registers emulate the 16550 UART and enable the
PC/XT/AT to interface with them as with an actual 16550
UART. This allows the Z80182/Z8L182 to be software
compatible with existing modem software.
D7 D6 D5 D4 D3 D2 D1 D0
0000000 0
Receive Buffer Register
Figure 69. Receive Buffer Register
(PC Read Only, Address 00H, DLAB=0, R/W=Read)
(Z180^™ MPU Write Only, Address XXF0H)
Receive Buffer Register
When the Z180 has assembled a byte of data to pass to the
PC/XT/AT, it places it in the Receive Buffer Register. If the
Received Data Available interrupt is enabled then an
interrupt is generated for the PC/XT/AT and the Data Ready
bit is set (if the Receive Timer is enabled, the interrupt and
setting of the Data Ready bit is delayed until after the timer
times out). Also the shadowed bits of the Line Status
Register are transferred to their respective bits when the
Z180 MPU writes to the Receive Buffer Register (See Line
Status Register Bits 1, 2, 3 and 4). This allows a simultaneous
setting of error bits when the data is written to the Receive
Buffer Register. In FIFO, mode this address is used to read
(PC) and write (Z180) the Receive FIFO.
D7 D6 D5 D4 D3 D2 D1 D0
0000000 0
Transmitter Holding Register
Figure 70. Transmit Holding Register
(PC Write Only, Address 00H, DLAB=0, R/W=Write)
(Z180 MPU Read Only, Address xxF0H)
Transmit Holding Register
When the PC/XT/AT writes to the Transmit Holding Register,
the Z80182/Z8L182 responds by setting the appropriate
bit in the IP register and by generating an interrupt to the
Z180 MPU if it is enabled. When the Z180 MPU reads this
register the Transmit Holding Register empty flag is set (if
the transmitter timer is enabled , this bit is set after the timer
times out). In FIFO mode of operation, this address is used
to read (Z180) and write (PC) the Transmitter FIFO.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 000000
FIFO Enable
RCVR FIFO Reset
XMIT FIFO Reset
DMA Mode Select
Reserved (Tx Overrun, MPU only)
Reserved (FCR Write, MPU only)
RCVR Trigger (LSB)
RCVR Trigger (MSB)
Figure 71. FIFO Control Register
(PC Write Only, Address 02H)
(Z180 MPU Read Only, Address xxE9H)
DS971820600
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