Z80182 Datasheet, PDF (11/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
MULTIPLEXED PIN DESCRIPTIONS
A18/T During Reset, this pin is initialized as an A18 pin.
OUT.
If either TOC1 or TOC0 bit of the Timer Control Register
(TCR) is set to 1, The T function is selected. If TOC1 and
OUT
TOC0 bits are cleared to 0, the A18 function is selected.
In normal user mode (on-chip bus master), the A18 signal
for the chip select logic is obtained from the CPU before
the external pin is muxed as A18/T . Therefore, the
OUT
selection of T will not affect the operation of the 182 chip
OUT
select logic. However, in adapter mode (off-chip bus
master), the A18 signal MUST be provided by the external
bus master.
CKA0//DREQ0. During Reset, this pin is initialized as
CKA0 pin. If either DM1 or SM1 in the DMA Mode Register
(DMODE) is set to 1, /DREQ0 function is always selected.
Bit 1
0
0
1
1
Table 2. Triple Multiplexed Pins
Bit 2
Master Configuration Register
0
/TEND1,TxS,CKS
1
/RTSB,/DTR//REQB,/W//REQB
0
/TEND1,TxS,CKS
1
/HRxRDY,//HTxRDY,HINTR
The pins below are multiplexed based upon the value of bit
1 of the System Configuration register. If bit 1 is 0, then the
Z80182/Z8L182 Mode 0 (non-16550 MIMIC mode) signals
are selected; if bit 1 is 1, then Z80182/Z8L182 Mode 1
(16550 MIMIC mode) signals are selected. On Reset,
Z80182/Z8L182 Mode 0 is always selected as shown in
Table 3.
CKA1//TEND0. During Reset, this pin is initialized as
CKA1 pin. If CKA1D bit in the ASCI control register
Ch1(CNTLA1) is set to 1, /TEND0 function is selected. If
CKA1D bit is set to 0, CKA1 function is selected.
RxS//CTS1. During Reset, this pin is initialized as the RxS
pin. If CTS1E bit in the ASCI status register Ch1 (STAT1) is
set to 1, /CTS1 function is selected. If CTS1E bit is set to 0,
RxS function is selected. This pin is also multiplexed with
PB7 based on bit 6 in the System Configuration Register.
The pins below are triple-multiplexed based upon the
values of bit 1 and bit 2 of the System Configuration
Register. The pins are configured as Table 2 specifies. On
Reset, both bits 1 and 2 are 0, so /TEND1,TxS,CKS are
selected.
Table 3. Mode 0 and Mode 1 Multiplexed Pins
Z80182/Z8L182
Mode 0
Z80182/Z8L182
Mode 1
TxDB
RxDB
/TRxCB
/RTxCB
/SYNCB
/CTSB
/DCDB
PA7-PA0
/HDDIS
HA1
HA0
HA2
/HCS
/HWR
/HRD
HD7-HD0
DS971820600
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