Z80182 Datasheet, PDF (42/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
MMU REGISTERS
CBR
Addr 38H
Bit CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
Upon Reset
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
MMU Common Base
Register
Figure 43. MMU Common Base Register
BBR
Addr 39H
Bit BB7 BB6 BB5 BB4 BB3 BB2 BB1 BB0
Upon Reset
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
MMU Bank Base Register
Figure 44. MMU Bank Base Register
CBAR
Addr 3AH
Bit CA3 CA2 CA1 CA0 BA3 BA2 BA1 BA0
Upon Reset
1
1
1
1
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
MMU Bank Area Register
MMU Common Area Register
Figure 45. MMU Common/Bank Area Register
3-42
DS971820600