Z80182 Datasheet, PDF (18/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z85230 ESCC^™ FUNCTIONAL DESCRIPTION
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
The Zilog Enhanced Serial Communication Controller
ESCC^™is a dual channel, multiprotocol data communication
peripheral. The ESCC functions as a serial-to-parallel,
parallel-to-serial converter/controller. The ESCC can be
software-configured to satisfy a wide variety of serial
communications applications. The device contains a variety
of new, sophisticated internal functions including on-chip
baud rate generators, digital phase-lock loops, and crystal
oscillators, which dramatically reduce the need for external
logic.
The ESCC handles asynchronous formats, synchronous
byte-oriented protocols such as IBM^® Bisync, and
synchronous bit-oriented protocols such as HDLC and
IBM SDLC. This versatile device supports virtually any
serial data transfer application (telecommunication, LAN,
etc.)
The device can generate and check CRC codes in any
synchronous mode and can be programmed to check
data integrity in various modes. The ESCC also has facilities
for modem control in both channels in applications where
these controls are not needed, the modem controls can be
used for general-purpose I/O.
With access to 14 Write registers and 7 Read registers per
channel (number of the registers varies depending on the
version), the user can configure the ESCC to handle all
synchronous formats regardless of data size, number of
stop bits, or parity requirements. The ESCC also
accommodates all synchronous formats including
character, byte, and bit-oriented protocols.
The ESCC (Enhanced SCC) is pin and software compatible
to the CMOS SCC version. The following enhancements
were made to the CMOS SCC:
s Deeper Transmit FIFO (4 bytes)
s Deeper Receive FIFO (8 bytes)
s Programmable FIFO interrupt and DMA request level
s Seven enhancements to improve SDLC link layer
supports:
- Automatic transmission of the opening flag
- Automatic reset of Tx Underrun/EOM latch
- Deactivation of /RTS pin after closing flag
- Automatic CRC generator preset
- Complete CRC reception
- TxD pin automatically forced High with NRZI
encoding when using mark idle
- Status FIFO handles better frames with an ABORT
- Receive FIFO automatically unlocked for special
receive interrupts when using the SDLC status FIFO
s Delayed bus latching for easier microprocessor
interface
s New programmable features added with Write Register
7' (WR seven prime)
s Write registers, 3, 4, 5 and 10 are now readable
s Read register 0 latched during access
Within each operating mode, the ESCC also allows for
protocol variations by checking odd or even parity bits,
character insertion or deletion, CRC generation, checking
break and abort generation and detection, and many other
protocol-dependent features.
s DPLL counter output available as jitter-free transmitter
clock source
s Enhanced /DTR, /RTS deactivation timing
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DS971820600