Z80182 Datasheet, PDF (90/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
TIMING DIAGRAMS (Continued)
PRELIMINARY
T1
T2
TW
T3
0
Address
/MREQ
/RD
/WR
/MRD
/MWR
Address Valid
7
8
9
13
24
22
7
13
9
7
24
22
Figure 101. /MWR and /MRD Timing
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
T1
11
11
11
65
66
EXTAL
VIL1
VIH1
VIH1
VIL1
Figure 102. External Clock Rise Time and Fall Time
70
69
Figure 103. Input Rise and Fall Time
(Except EXTAL, /RESET)
3-90
DS971820600