Z80182 Datasheet, PDF (34/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
ASCI CHANNELS CONTROL REGISTERS (Continued)
TDR0
Write Only
Addr 06H
7 6 5 4 32 1 0
TSR1
Read Only
Addr 09H
xxxxxxxx
Transmit Data
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Received Data
Figure 15. ASCI Transmit Data Register (Ch. 0)
Figure 18. ASCI Receive Data Register (Ch. 1)
TDR1
Write Only
Addr 07H
7 6 5 4 3 2 10
Transmit Data
Figure 16. ASCI Transmit Data Register (Ch. 1)
TSR0
Read Only
Addr 08H
xxxxxxxx
Received Data
Figure 17. ASCI Receive Data Register (Ch. 0)
BRK0
Read/Write
Addr 12H
76543210
Break generate bit
0 = no break
1 = break
Break detect bit
0 = no break
1 = break
Break feature bit
0 = dissolve
1 = enable
Figure 19. ASCI Break Control Register (Ch. 0)
BRK1
Read/Write
Addr 13H
76543210
Break generate bit
0 = no break
1 = break
Break detect bit
0 = no break
1 = break
Break feature enable bit
0 = disable
1 = enable
Figure 20. ASCI Break Control Register (Ch. 1)
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DS971820600