Z80182 Datasheet, PDF (106/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
16550 MIMIC TIMING (Continued)
Table M. RCVR FIFO Bytes Other Than First
No
Sym
Parameter
Z8L182
20 MHz
Min
Max
Z80182
33 MHz
Min
Max
Units
19
tRXi
Delay from /HRD
RBR to /HRxRDY Inactive
20
TWxi
Delay from Write to
/HTxRDY Inactive
21
tSXa
Delay From Start to
/HTxRDY Active
290
125
3 MPU
Clock Cycles
Note:
These AC parameter values are preliminary and are subject to change without notice.
290
ns
125
3 MPU
Clock Cycles
Clock Generator
The Z80182/Z8L182 ZIP^™ uses the Z182 MPUs on-chip
clock generator to supply system clock. The required
clock is easily generated by connection a crystal to the
external terminals (XTAL,EXTAL). The clock output runs at
half the crystal frequency for X2 mode.
Recommended characteristics of the crystal and the values
for the capacitor are as follows (the values will change with
crystal frequency).
Type of crystal:
Fundamental, parallel type crystal
(AT cut is recommended).
Frequency tolerance:
Application dependent.
RS, equivalent-series resistance:
≤ 60 Ohms
C =C =15~22 pF.
IN OUT
For PHI > 15 MHz (X2 Mode), it is recommended that an
oscillator be used as input to EXTAL.
C1
XTAL
Crystal
Inputs
C2
EXTAL
CL, Load capacitance:
Approximately 22 pF
(acceptable range is 20-30 pF).
Figure 117. Circuit Configuration For Crystal
3-106
DS971820600