Z80182 Datasheet, PDF (92/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z8S180 AC CHARACTERISTICS (Continued)
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
No. Sym
Parameter
Z8L180
20 MHz
Min Max
Z8S180
33 MHz
Min Max
Unit Note
41 tRFD1
42 tRFD2
43 tHAD1
44 tHAD2
45 tDRQS
Clock Rise to /RFSH Fall Delay
Clock Rise to /RFSH Rise Delay
Clock Rise to /HALT Fall Delay
Clock Rise to /HALT Rise Delay
/DREQi Setup Time to Clock Rise
20
20
15
15
20
15
ns
15
ns
15
ns
15
ns
15
ns
46 tDRQH
47 tTED1
48 tTED2
49 tED1
50 tED2
/DREQi Hold Time from Clock Rise
Clock Fall to /TENDi Fall Delay
Clock Fall to /TENDi Rise Delay
Clock Rise to E Rise Delay
Clock Edge to E Fall Delay
20
25
25
30
30
15
ns
15
ns
15
ns
15
ns
15
ns
51 PWEH
52 PWEL
53 tEr
54 tEf
55 tTOD
E Pulse Width (High)
E Pulse Width (Low)
Enable Rise Time
Enable Fall Time
Clock Fall to Timer Output Delay
25
50
10
10
75
20
ns
40
ns
10
ns
10
ns
50
ns
56 tSTDI
57 tSTDE
58 tSRSI
CSI/O Tx Data Delay Time
(Internal Clock Operation)
CSI/O Tx Data Delay Time
(External Clock Operation)
CSI/O Rx Data Setup Time
(Internal Clock Operation)
75
7.5 tcyc+100
1
1
60
ns
7.5 tcyc+100 ns
tcyc
59 tSRHI
60 tSRSE
61 tSRHE
CSI/O Rx Data Hold Time
(Internal Clock Operation)
CSI/O Rx Data Setup Time
(External Clock Operation)
CSI/O Rx Data Hold Time
(External Clock Operation)
1
1
tcyc
1
1
tcyc
1
1
tcyc
62 tRES
63 tREH
64 tOSC
65 tEXr
/RESET Setup time to Clock Fall
/RESET Hold time from Clock Fall
Oscillator Stabilization Time
External Clock Rise Time (EXTAL)
40
25
20
10
25
ns
15
ns
20
ms
5
ns
66 tEXf
External Clock Fall Time (EXTAL)
10
67 tRr
/RESET Rise Time
50
68 tRf
/RESET Fall Time
50
69 tIr
Input Rise Time (Except EXTAL, /RESET)
50
70 tIf
Input Fall Time (Except EXTAL, /RESET)
50
71 TdCS
/MREQ Valid to /ROMCS, /RAMCS Valid Delay
15
72 TdIOCS
/IORQ Valid to /IOCS Valid Delay
15
5
ns
50
ms [2]
50
ms [2]
50
ns [2]
50
ns [2]
10
ns
10
ns
Notes:
These AC parameters values are preliminary and subject to change without notice.
[1] All specifications reflect 100% output drive (disabled slew rate limiting feature).
[2] Specification 1 through 5 refer to PHI clock output.
[3] Exceeds characterization (data propagation delay needs to be analyzed).
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DS971820600