Z80182 Datasheet, PDF (102/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
16550 MIMIC TIMING (Continued)
HD7-HD0
Valid
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
/HWR
7
8
9
Figure 111. Data Setup and Hold, Output Delay, Write Cycle
HD7-HD0
Valid
/HRD
11
10
12
Figure 112. Data Setup and Hold, Output Delay, Read Cycle
Table I. Data Setup and Hold, Output Delay, Read Cycle
No. Sym
Parameter
Z8L182
20 MHz
Min
Max
Z80182
33 MHz
Min
Max
7
tDs
8
tDh
9
tWc
10
tRvD
11
tHz
12
tRc
Data Setup Time
Data Hold Time
Write Cycle Delay
Delay from /HRD to Data
/HRD to Floating Delay
Read Cycle Delay
30
30
2.5 MPU
Clock Cycles
125
100
125
Note:
These AC parameter values are preliminary and are subject to change without notice.
30
30
2.5 MPU
Clock Cycles
125
100
125
Units
ns
ns
ns
ns
ns
ns
3-102
DS971820600