Z80182 Datasheet, PDF (17/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Z182 CPU
The Z182 CPU is 100% software compatible with the Z80^®
CPU and has the following additional features:
Faster Execution Speed. The Z182 CPU is “fine tuned,”
making execution speed, on average, 10% to 20% faster
than the Z80 CPU.
Enhanced DRAM Refresh Circuit. Z182 CPU’s DRAM
refresh circuit does periodic refresh and generates an
8-bit refresh address. It can be disabled or the refresh
period adjusted, through software control.
Enhanced Instruction Set. The Z182 CPU has seven
additional instructions to those of the Z80 CPU, which
include the MLT (Multiply) instruction.
HALT and Low Power Modes of Operation. The Z182
CPU has HALT and Low Power modes of operation, which
are ideal for the applications requiring low power
consumption like battery operated portable terminals.
System Stop Mode. When the Z182 is in System Stop
mode, it is only the Z180 MPU that is in STOP mode.
Standby and Idle Mode. Please refer to the Z8S180
Product Specification for additional information on these
two additional Low Power modes.
Instruction Set. The instruction set of the Z182 CPU is
identical to the Z180. For more details about each
transaction, please refer to the Product Specification/
Technical Manual for the Z180/Z80 CPU.
Z182 CPU Basic Operation
Z182 CPU’s basic operation consists of the following
events. These are identical to the Z180 MPU. For more
details about each operation, please refer to the Product
Specification/Technical Manual for the Z180.
s Operation Code Fetch Cycle
s Memory Read/Write Operation
s Input/Output Operation
s Bus Request/Acknowledge Operation
s Maskable Interrupt Request Operation
Memory Management Unit (MMU)
The Memory Management Unit (MMU) allows the user to
map the memory used by the CPU (64 Kbytes of logical
addressing space) into 1 Mbyte of physical addressing
space. The organization of the MMU allows object code
compatibility with the Z80 CPU while offering access to an
extended memory space. This is accomplished by using
an effective common area-banked area scheme.
DMA Controller
The Z182 MPU has two DMA controllers. Each DMA
controller provides high-speed data transfers between
memory and I/O devices. Transfer operations supported
are memory-to-memory, memory-to/from-I/O, and I/O-to-
I/O. Transfer modes supported are request, burst, and
cycle steal. The DMA can access the full 1 Mbytes
addressing range with a block length up to 64 Kbytes and
can cross over 64K boundaries.
Asynchronous Serial Communication Interface
(ASCI)
This unit provides two individual full-duplex UARTs. Each
channel includes a programmable baud rate generator
and modem control signals. The ASCI channels also
support a multiprocessor communication format.
Programmable Reload Timer (PRT)
The Z182 MPU has two separate Programmable Reload
Timers, each containing a 16-bit counter (timer) and count
reload register. The time base for the counters is system
clock divided by 20. PRT channel 1 provides an optional
output to allow for waveform generation.
Clocked Serial I/O (CSI/O)
The CSI/O channel provides a half-duplex serial transmitter
and receiver. This channel can be used for simple high-
speed data connection to another CPU or MPU.
Programmable Wait State Generator
To ease interfacing with slow memory and I/O devices, the
Z182 MPU unit has a programmable wait state generator.
By programming the DMA/WAIT Control Register (DCNTL),
up to three wait states are automatically inserted in memory
and I/O cycles. This unit also inserts wait states during on-
chip DMA transactions. When using RAMCS and ROMCS
wait state generators, the wait state controller with the
most programmed wait states will determine the number of
wait states inserted.
s Trap and Non-Maskable Interrupt Request Operation
s HALT and Low Power Modes of Operation
s Reset Operation
DS971820600
3-17