Z80182 Datasheet, PDF (32/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
ASCI CHANNELS CONTROL REGISTERS (Continued)
Bit
Upon Reset
R/W
CNTLB1
MPBT MP
Invalid 0
R/W R/W
/CTS/
PS
0
R/W
PE0
0
R/W
Addr 03H
DR SS2 SS1 SS0
0
1
1
1
R/W R/W R/W R/W
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Clock Source and Speed Select
Divide Ratio
Parity Even or Odd
Read - Status of /CTS pin
Write - Select PS
Multiprocessor
Multiprocessor Bit Transmit
General
Divide Ratio
SS, 2, 1, 0
PS = 0
(Divide Ratio = 10)
DR = 0 (x16)
DR = 1 (x64)
000
001
010
011
100
101
110
*111
Ø ÷ 160
Ø ÷ 640
Ø ÷ 320
Ø ÷ 1280
Ø ÷ 640
Ø ÷ 2580
Ø ÷ 1280
Ø ÷ 5120
Ø ÷ 2560
Ø ÷ 10240
Ø ÷ 5120
Ø ÷ 20480
Ø ÷ 10240
Ø ÷ 40960
External Clock (Frequency < Ø ÷ 40)
Note:
* Baud rate is external clock rate ÷ 16; therefore, Ø ÷ (40 x 16)
is maximum baud rate using external clocking.
PS = 1
(Divide Ratio = 30)
DR = 0 (x16)
Ø ÷ 480
Ø ÷ 960
Ø ÷ 1920
Ø ÷ 3840
Ø ÷ 7680
Ø ÷ 15360
Ø ÷ 30720
Figure 12. ASCI Control Register B (Ch. 1)
DR = 1 (x64)
Ø ÷ 1920
Ø ÷ 3840
Ø ÷ 7680
Ø ÷ 15360
Ø ÷ 30720
Ø ÷ 61440
Ø ÷ 122880
3-32
DS971820600