Z80182 Datasheet, PDF (16/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Z80182/Z8L182 FUNCTIONAL DESCRIPTION
Functionally, the on-chip Z182 MPU and ESCC^™ are the
same as the discrete devices (Figure 1). Therefore, for a
detailed description of each individual unit, refer to the
Product Specification/Technical Manuals of each discrete
product. The following subsections describe each of the
individual units of the Z182.
Z182 MPU FUNCTIONAL DESCRIPTION
This unit provides all the capabilities and pins of the Zilog
Z8S180 MPU (Static Z80180 MPU). Figure 4 shows the
S180 MPU Block Diagram of the Z182. This allows 100%
software compatibility with existing Z180^™ (and Z80^®)
software. The following is an overview of the major functional
units of the Z182.
Timing &
Ø
Clock
Generator
A18
/TOUT
16-Bit
Programmable
Reload Timers
(2)
TxS
RxS//CTS
CKS
Clocked
Serial I/O
Port
MMU
Bus State Control
CPU
DMACs
(2)
Interrupt
/DREQ1
/TEND
Asynchronous
SCI
(Channel 0)
Asynchronous
SCI
(Channel 1)
TxA0
CKA0 /DREQ0
RxA0
/RTS0
/CTS0
/DCD0
TxA1
CKA1 /TEND0
RxA1
A19-A0
D7-D0
Figure 4. S180 MPU Block Diagram of Z182
3-16
DS971820600