Z80182 Datasheet, PDF (100/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
ESCC External Bus Master Timing
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Valid ESCC
Addr * IORQ
/RD or
/WR
DTR/REQ
Request
1
2
Figure 109. ESCC External Bus Master Timing
Table G. External Bus Master Interface Timing (SCC Related Timing)
No. Symbol
Parameter
Z8L182
20 MHz
Min Max
Z80182
33 MHz
Min Max
1 TrC
2 TdRDr(REQ)
Valid Access Recovery Time
/RD Rise to /DTR//REQ Not Valid Delay
4TcC
4TcC
Notes:
These AC parameter values are preliminary and are subject to change without notice.
[1] Applies only between transactions involving the ESCC.
T = ESCC clock period time
CC
4TcC
4TcC
Units
ns
ns
Notes
[1]
3-100
DS971820600