Z80182 Datasheet, PDF (104/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
16550 MIMIC TIMING (Continued)
Table K. Interrupt Timing RCVR FIFO
No. Sym
Parameter
Z8L182
20 MHz
Min
Max
14
tSINT
Delay from Stop to Set
Interrupt
2 MPU
Clock Cycles
15
tRINT
Delay from /HRD
(RD RBR or RD LSR)
to Reset Interrupt
2 MPU
Clock Cycles
Note:
These AC parameter values are preliminary and are subject to change without notice.
/RD (MPU)
TxFIFO
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Z80182
33 MHz
Min
Max
2 MPU
Clock Cycles
2 MPU
Clock Cycles
HINTR
THRE
/WR (Host)
THR
/RD (Host)
11R
17
16
18
Figure 115. Interrupt Timing Transmitter FIFO
3-104
DS971820600