Z80182 Datasheet, PDF (27/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
PARALLEL PORTS FUNCTIONAL DESCRIPTION
The Z80182/Z8L182 has three 8-bit bi-directional Ports.
Each bit is individually programmable for input or output
(with the exception of PC6 and PC7 which are inputs only).
The Ports are controlled through two registers: the Port
Direction Control Register and the Port Data Register.
(Please see register description for Ports A, B and C).
PROGRAMMING
The following subsections explain and define the
parameters for I/O Address assignments. The three tables
in this section describe the mapping of the common
registers shared by the MPU and the 16550 MIMIC. The
MPU address refers to the I/O address as accessed from
the MPU side (the Z180^™ MPU interface side of the 16550
MIMIC). Note that only the lowest eight address lines are
decoded for Z182 peripheral access. The full sixteen
address lines are decoded for on-chip Z180 MPU access.
The PC address (coined because the UART is common in
PCs) is the address needed to access the MIMIC registers
through the MIMIC interface signals. The MIMIC interface
signals are multiplexed with the ESCC channel B and the
Port A signals, and must be activated through the System
Configuration Register and the Interrupt Edge/Pin MUX
Register.
Table 7. Z80182/Z8L182 MPU Registers
Register Name
MPU Addr
Z80182/Z8L182 MPU Control Registers
Note:
“x” indicates don’t care condition
0000H to 00x3FH
(Relocatable to 0040H to 007FH
or 0080H to 00BFH)
PC Addr
None
Table 8. Z80182/Z8L182 MIMIC Register MAP
Register Name
MPU Addr/Access
PC Addr/Access
MMC MIMIC Master Control Register
IUS/IP Interrupt Pending
IE Interrupt Enable
IVEC Interrupt Vector
TTCR Transmit Time Constant
RTCR Receive Time Constant
FSCR FIFO Status and Control
RTTC Receive Timeout Time Constant
TTTC Transmit Timeout Time Constant
RBR Receive Buffer Register
THR Transmit Holding Register
IER Interrupt Enable Register
IIR Interrupt Identification
FCR FIFO Control Register
MM REGISTER
LCR Line Control Register
MCR Modem Control Register
LSR Line Status Register
MSR Modem Status Register
SCR Scratch Register
DLL Divisor Latch (LSByte)
DLM Divisor Latch (MSByte)
xxFFH
xxFEH
xxFDH
xxFCH
xxFAH
xxFBH
xxECH
xxEAH
xxEBH
xxF0H
xxF0H
xxF1H
None
xxE9H
XXE9H
xxF3H
xxF4H
xxF5H
xxF6H
xxF7H
xxF8H
xxF9H
R/W
R/Wb7
R/W
R/W
R/W
R/W
R/W7-4
R/W
R/W
W only
R only
R only
R only
W only
R only
R only
R/Wb6432
R/Wb7-4
R only
R only
R only
None
None
None
None
None
None
None
None
None
00H
00H
01H
02H
02H
None
03H
04H
05H
06H
07H
00H
01H
DLAB=0 R only
DLAB=0 W only
DLAB=0 R/W
R only
W only
R/W
R/W
R only
R only
R/W
DLAB=1 R/W
DLAB=1 R/W
DS971820600
3-27