Z80182 Datasheet, PDF (22/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
16550 MIMIC FIFO DESCRIPTION
The receiver FIFO consists of a 16-word FIFO capable of
storing eight data bits and three error bits for each character
stored (Figure 7). Parity error, Framing error and Break
detect bits are stored along with the data bits by copying
their value from three shadow bits that are Write Only bits
for the Z80180 MPU LSR address. The three shadow bits
are cleared after they are copied to the FIFO memory. In
FIFO mode, to write error bits into the receiver FIFO, the
MPU must first write the Parity, Framing and Break detect
status to the Line Status Register (shadow bits) and then
write the character associated into the receiver buffer. The
data and error bits will then move into the same address in
the FIFO. The error bits become available to the PC side of
the interface when that particular location becomes the
next address to read (top of FIFO). At that time, they may
either be read by the PC by accessing them in the LSR, or
they may cause an interrupt to the PC interface if so
enabled. The error bits are set by the error status of the byte
at the top of the FIFO, but may only be cleared by reading
the LSR. If successive reads of the receiver FIFO are
performed without reading the LSR, the status bits will be
set if any of the bytes read have the respective error bit set.
See Table 6 for the setting and clearing of the Line Status
Register bits.
MPU Write
LSR Shadow
B2-B4
error
3
3
PC Read
LSR
B2-B4
MPU
CNTL
Line
Internal Clock
Sync
MPU
8
Databus
(MPU Side Write)
Internal Clock
W
R
I
T
E
B
U
F
F
E
R
Write
Pointer
16x8
Data Bits
ALU
MPU
IRQ
16x3 R
Error E
Bits A
D
B
U
F
F
E
R
Read
Pointer
Internal Clock
PC
Cntrl
Line
Sync
8
PC Side
Databus
(PC Side Read)
5
FIFO Control
Register
PC
IRQ
MPU Side
Interface
Figure 7. 16550 MIMIC Receiver FIFO Block Diagram
16550
MIMIC or
PC Side
Interface
3-22
DS971820600