DS617 Datasheet, PDF (80/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

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Platform Flash XL High-Density Configuration and Storage Device
Table 46: Command Interface States – Modify Table, Next State⁽¹⁾ (Cont’d)
Command Input
Current CI State
Buffer
Program
in Erase
Suspend
(Cont’d)
Suspend
IS in BP
Suspend
in ES
BP
Suspend
in ES
IS in BP
Suspend
in ES
BP
Suspe
nd in
ES
IS in BP
BP
Suspend in Suspend
Erase Suspend in ES
Buffer Program Suspend in Erase Suspend
BP Suspend in Erase Suspend
Setup
Ready (error)
Ready (error)
Blank
Check
Lock/CR
Setup in
Erase
Suspend
Buffer
EFP
Busy
Setup
Busy
Blank
Check
busy
IS in
Blank
Check
busy
Blank
Check
busy
IS in Blank
Check busy
Blank Check busy
Erase Suspend (Lock Error)
Erase Suspend
Erase Suspend (Lock Error)
Ready (error)
BEFP
Busy
BEFP Busy⁽⁶⁾
Ready (error)
Notes:
1. CI = Command Interface: CR = Configuration register: BEFP = Buffer Enhanced Factory program: P/E C = Program/Erase controller: IS =
Illegal State: BP = Buffer Program: ES = Erase Suspend.
2. At power-up, all banks are in Read Array mode. Issuing a Read Array command to a busy bank, results in undetermined data output.
3. The two cycle command should be issued to the same bank address.
4. If the P/E C is active, both cycles are ignored.
5. The Clear Status Register command clears the SR error bits except when the P/E C. is busy or suspended.
6. BEFP is allowed only when Status Register bit SR0 is reset to '0'. BEFP is busy if Block Address is first BEFP Address. Any other commands
are treated as data.
7. Buffer Program will fail at this point if any block address is different from the first address.
DS617 (v3.0.1) January 07, 2010
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Product Specification
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