DS617 Datasheet, PDF (3/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Flash Memory Architecture Overview
Platform Flash XL is a 128-Mb (8 Mb × 16) non-volatile flash
memory. The device is in-system programmable with a 1.8V
core (V_DD) power supply. A separate I/O (V_DDQ) power supply
enables I/O operation at 3.3V or 2.5V. An optional 9V V_PP
power supply can accelerate factory programming.
A common flash interface (CFI) provides access to device
memory (Figure 3, page 3). Moreover, Platform Flash XL
supports multiple read modes. A 23-bit address bus
provides random read access to each 16-bit word. Four
words occupy each page for accelerated page mode reads.
The device powers-up in a synchronous burst read mode
capable of sequential read rates up to 54 MHz.
Platform Flash XL has a multiple-bank architecture. An array of
131 individually erasable blocks are divided into 16, 8-Mb
banks. Fifteen main banks contain uniform blocks of
64 Kwords, and one parameter bank contains seven main
blocks of 64 Kwords, plus four parameter blocks of 16 Kwords.
Note: The device is electronically erasable at the block level and
programmable on a word-by-word basis.
The multiple-bank architecture allows dual operations —
read operations can occur on one bank while a program or
erase operation occurs in a different bank. However, only
one bank at a time is allowed to be in program or erase
mode. Burst reads are allowed to cross bank boundaries.
Table 1 summarizes the bank architecture, and the memory
map is shown in Figure 4, page 5. The parameter blocks are
located at the top of the memory address space in Platform
Flash XL.
Table 1: Bank Architecture
Number
Bank Size
Parameter
Bank
8 Mbits
Parameter
Blocks
4 blocks of
16 Kwords
Bank 1
8 Mbits
–
Bank 2
8 Mbits
–
Bank 3
8 Mbits
–
Main Blocks
7 blocks of
64 Kwords
8 blocks of
64 Kwords
8 blocks of
64 Kwords
8 blocks of
64 Kwords
Bank 14
Bank 15
8 Mbits
8 Mbits
–
8 blocks of
64 Kwords
–
8 blocks of
64 Kwords
Each block can be erased separately. Erase operations can
be suspended in order to perform a program or read operation
in any other block and then resumed. Program operations can
be suspended to read data at any memory location except for
the one being programmed, and then resumed.
Program and erase commands are written to the command
interface of the memory. An internal program/erase
controller takes care of the timing necessary for program
and erase operations. The end of a program or erase
operation can be detected and any error conditions
identified in the status register. The command set required
to control the memory is consistent with JEDEC standards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory array. At
power-up, the device is configured for synchronous read. In
synchronous burst read mode, data is output on each clock
cycle at frequencies of up to 54 MHz. The synchronous
burst read operation can be suspended and resumed.
When the bus is inactive during asynchronous read
operations, the device automatically switches to an
automatic standby mode. In this condition the power
consumption is reduced to the standby value, and the
outputs are still driven.
Platform Flash XL features an instant, individual block-
locking scheme, allowing any block to be locked or unlocked
with no latency, and enabling instant code and data
protection. All blocks have three levels of protection. Blocks
can be locked and locked-down individually preventing any
accidental programming or erasure. There is an additional
hardware protection against program and erase: when V_PP
= V_PPLK all blocks are protected against program or erase.
All blocks are locked at power-up.
The device features a separate region of 17 programmable
registers whose values can be protected against further
programming changes. Sixteen of these registers are each
128-bits in size, with the 17^th register subdivided into two 64-
bit registers. One of the 64-bit registers contains a factory
preprogrammed, unique device number, permanently
protected against modification. The second 64-bit register is
user-programmable.
All bits within these registers (except for the permanently-
protected unique number register) are one-time-
programmable (OTP) — each bit can be programmed only
once from a one-value to a zero-value.
Two protection lock registers can be programmed to lock any
of the 17 protectable registers against further changes. One
protection lock register contains bits that determine the
protection state of the two special 64-bit registers. The bit
corresponding to the unique device number register is pre-
programmed to ensure the unique device number register is
permanently protected against modification. The second
protection lock register contains OTP bits that correspond
the protection state each of the remaining 16 registers.
Platform Flash XL is available in a 10 × 13 mm, 1.0 mm-pitch
FT64 package and supplied with all the bits erased (set to '1').
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
3