DS617 Datasheet, PDF (38/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
X-Ref Target - Figure 18
V_DD
V_DDPOR
V_DDPD
Platform Flash XL High-Density Configuration and Storage Device
T_VDDPOR(MIN)
Recommended Operating Voltage Range
Delay FPGA
Configuration⁽¹⁾
50 ^{ms Ramp}
T_VDDPOR(MAX)
T
VHRWZ
T
VHRWZ
T
RST
Time
DS617_14_101608
Notes:
1. A slow-ramping V_DD power supply can still be below the minimum operating voltage when the READY_WAIT pin is released. In this case, the
configuration sequence must be delayed until both V_DD and V_DDQ have reached their recommended operating conditions.
2. For FPGA configuration via Master-BPI mode, the supplies V_DD and V_DDQ must reach their respective recommended operating conditions
before the start of the FPGA configuration procedure.
Figure 18: V_DD Behavior During the Power-Up Sequence or Brownout
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
38