DS617 Datasheet, PDF (5/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Pinout and Signal Descriptions
See Figure 5 and Table 2 for a logic diagram and brief overview of the signals connected to this device.
Table 2: Signal Names
Signal Name
Function
A22-A0
Address Inputs
DQ15-DQ0
Data Input/Outputs,
Command Inputs
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset
WP
Write Protect
K
Clock
L
Latch Enable
READY_WAIT
Ready/Wait
V_DD
V_DDQ
V_PP
Supply Voltage
Supply Voltage for
Input/Output Buffers
Optional⁽¹⁾ Supply
Voltage for Fast
Program and Erase
V_SS
V_SSQ
Ground
Ground Input/output
Supply
NC
Not Connected
Internally
Direction
Inputs
I/O
Input
Input
Input
Input
Input
Input
Input
I/O
–
–
–
–
–
–
X-Ref Target - Figure 5
V_DD V_DDQ V_PP
23
A22–A0
W
E
G
RP
WP
L
K
16
DQ15–DQ0
Platform
Flash XL
READY_WAIT
V_SS
V_SSQ
Figure 5: Logic Diagram
DS617_05_053008
Notes:
1. Typically, V_PP is tied to the V_DDQ supply on a board. See the V_PP
Program Supply Voltage section for alternate options.
Address Inputs (A22-A0)
The Address inputs select the words in the memory array to
access during Bus Read operations. During Bus Write
operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ15-DQ0)
The Data I/O output the data stored at the selected address
during a Bus Read operation or input a command or the
data to be programmed during a Bus Write operation.
Chip Enable (E)
The Chip Enable input activates the memory control logic,
input buffers, decoders and sense amplifiers. When Chip
Enable is at V_IL and Reset is at V_IH, the device is in active
mode. When Chip Enable is at V_IH, the memory is
deselected, the outputs are high impedance, and the power
consumption is reduced to the standby level.
Output Enable (G)
The Output Enable input controls data outputs during the
Bus Read operation of the memory. Before the start of the
first address latching sequence (FALS), the Output Enable
input must be held Low before the clock starts toggling.
Write Enable (W)
The Write Enable input controls the Bus Write operation of
the memory’s Command Interface. The data and address
inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
5