DS617 Datasheet, PDF (48/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Table 28: Asynchronous Read AC Characteristics
Symbol
Alt
Parameter
T_AVAV
T_AVQV
T_AVQV1
T_AXQX(1)
T_ELTV
T_ELQV(2)
T_ELQX(1)
T_EHTZ
T_EHQX(1)
T_EHQZ(1)
T_GLQV(2)
T_GLQX(1)
T_GLTV
T_GHQX(1)
T_GHQZ(1)
T_GHTZ
T_AVLH
T_ELLH
T_LHAX
T_LLLH
T_LLQV
T_RC
T_ACC
T_PAGE
T_OH
T_CE
T_LZ
T_OH
T_HZ
T_OE
T_OLZ
T_OH
T_DF
T_AVADVH
T_ELADVH
T_ADVHAX
T_ADVLADVH
T_ADVLQV
Address valid to next address valid
Min
Address valid to output valid (random) Max
Address valid to output valid (page)
Max
Address transition to output transition Min
Chip enable Low to wait valid
Max
Chip enable Low to output valid
Max
Chip enable Low to output transition Min
Chip enable High to wait Hi-Z
Max
Chip enable High to output transition Min
Chip enable High to output Hi-Z
Max
Output enable Low to output valid
Max
Output enable Low to output transition Min
Output enable Low to wait valid
Max
Output enable High to output transition Min
Output enable High to output Hi-Z
Max
Output enable High to wait Hi-Z
Max
Address valid to latch enable High
Min
Chip enable Low to latch enable High Min
Latch enable High to address transition Min
Latch enable pulse width
Min
Latch enable Low to output valid
(random)
Max
Voltage Range
V_DDQ =
2.3V to 2.7V
V_DDQ =
3.0V to 3.6V
85
85
85
85
30
30
0
0
17
17
85
85
0
0
17
17
0
0
17
17
25
25
0
0
17
17
0
0
17
17
17
17
10
10
10
10
9
9
10
10
85
85
Notes:
1. Sampled only, not 100% tested.
2. G may be delayed by up to T_ELQV – T_GLQV after the falling edge of E without increasing t_ELQV.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
48