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DS617 Datasheet, PDF (54/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage
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Platform Flash XL High-Density Configuration and Storage Device
Table 30: Write AC Characteristics, Write Enable Controlled(1)
Symbol
Alt
Parameter
TAVAV
TWC Address Valid to Next Address Valid
Min
TAVLH
Address Valid to Latch Enable High
Min
TAVWH(2)
Address Valid to Write Enable High
Min
TDVWH
TDS Data Valid to Write Enable High
Min
TELLH
Chip Enable Low to Latch Enable High
Min
TELWL
TCS Chip Enable Low to Write Enable Low
Min
TELQV
Chip Enable Low to Output Valid
Min
TELKV
Chip Enable Low to Clock Valid
Min
TGHWL
Output Enable High to Write Enable Low
Min
TLHAX
Latch Enable High to Address Transition
Min
TLLLH
Latch Enable Pulse Width
Min
TWHAV(2)
Write Enable High to Address Valid
Min
TWHAX(2) TAH Write Enable High to Address Transition
Min
TWHDX TDH Write Enable High to Input Transition
Min
TWHEH TCH Write Enable High to Chip Enable High
Min
TWHEL(3)
Write Enable High to Chip Enable Low
Min
TWHGL
Write Enable High to Output Enable Low
Min
TWHLL(3)
Write Enable High to Latch Enable Low
Min
TWHWL TWPH Write Enable High to Write Enable Low
Min
TWLWH TWP Write Enable Low to Write Enable High
Min
TQVVPL
Output (Status Register) Valid to VPP Low
Min
TQVWPL
Output (Status Register) Valid to Write Protect Low Min
TVPHWH TVPS VPP High to Write Enable High
Min
TWHVPL
Write Enable High to VPP Low
Min
TWHWPL
Write Enable High to Write Protect Low
Min
TWPHWH
Write Protect High to Write Enable High
Min
Voltage Range
VDDQ =
2.3V to 2.7V
VDDQ =
3.0V to 3.6V
85
85
10
10
50
50
50
50
10
10
0
0
85
85
9
9
17
17
9
9
10
10
0
0
0
0
0
0
0
0
25
25
0
0
25
25
25
25
50
50
0
0
0
0
200
200
200
200
200
200
200
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept Low.
3. TWHEL and TWHLL have this value when reading in the targeted bank or when reading following a Set Configuration Register command.
System designers should take this timing into account and can insert a software No-Op instruction to delay the first read in the same bank after
issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the
command is a Read Array operation in a different bank and no changes to the Configuration Register are issued, TWHEL and TWHLL are 0 ns.
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
54
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