DS617 Datasheet, PDF (37/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

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Platform Flash XL High-Density Configuration and Storage Device
Power-On Reset
To ensure a correct power-up sequence of Platform Flash
XL, the V_DD ramp time, T_VDDPOR, must not be shorter than
200 μs or longer than 50 ms during power-up (see Figure 18,
page 40). These timing limits correspond to the ramp rate
values for which the power-up current is in the range where
the V_DD ramp time is formally characterized or tested.
The device requires that the V_DD power supply
monotonically rises to the nominal operating voltage within
the specified V_DD rise time. If the power supply cannot meet
this requirement, then the device might not perform power-
on reset properly.
During the POR sequence or a reset pulse (RP), the
READY_WAIT pin is held Low by the device. After the
required supply voltages (V_DD and V_DDQ) have reached
X-Ref Target - Figure 17
V_DD/V_DDQ
READY_WAIT
G
T_VHRWZ
T
RWRT
their respective POR thresholds, the READY_WAIT pin is
released after a minimum time of t_RWL, to give the power
supplies an additional margin for them to stabilize before
initiating the configuration.
For systems using a slow-rising power supply, an additional
power-monitoring circuit can be used to delay the release of
the READY_WAIT pin.
If the power drops below the power-down threshold
(V_DDPD), the device is reset and the READY_WAIT pin is
held Low again until the POR threshold is reached (see
Figure 18 for an illustration).
The power-up sequences with and without free-running
clock are represented in Figure 11, page 31 and Figure 17.
L
K
A22-A0 Address not Valid
DQ15–DQ0
T
AVKH3
1
T
KH3AX
2 34
Latency Cycles (default = 7)
Valid Address
FFFFh (Sync + Dummy Cycle)
T_KHQV
D0 D1 D2 D3 D4 D5
Notes:
1. W is tied High.
Figure 17: Power-Up Sequence (System with Free-Running Clock)
DS617_13_053008
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
37