DS617 Datasheet, PDF (7/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

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Platform Flash XL High-Density Configuration and Storage Device
Latch Enable (L)
Latch Enable latches the address bits on its rising edge.
The address latch is transparent when Latch Enable is at
V_IL and inhibited when Latch Enable is at V_IH.
The Latch Enable (L) signal must be held at V_IH during the
power-up phase, during the FALS restart phase and
through the entire FALS.
In asynchronous mode, the address is latched on L going
High. or addresses are sent continuously if L is held Low.
During Write operations, L can be tied Low (V_IL) to allow the
addresses to flow through.
Table 3: Latch Enable Logic Levels in Synchronous
and Asynchronous Modes
Operation
Asynchronous Synchronous
Bus Read
Bus Write
X
X or toggling
V_IH
X or toggling
Address Latch
Toggling
Toggling
Standby
X
X
Reset
V_IH
V_IH
FALS
V_IH
V_IH
Power-up
V_IH
V_IH
Notes:
1. See waveforms in the "DC and AC Parameters" section for
details.
Clock (K)
The Clock input synchronizes the memory to the FPGA
during synchronous read operations. The address is
latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V_IL. Clock is
ignored during asynchronous read and in write operations.
Ready/Wait (READY_WAIT)
Caution! The READY_WAIT requires an external pull-up
resistor to V_DDQ. The external pull-up resistor must be
sufficiently strong to ensure a clean, Low-to-High transition
within less than one microsecond (T_RWRT) when the
READY_WAIT pin is released to a high-impedance state.
READY_WAIT can perform one of two functions. By default,
READY_WAIT is an input/open-drain ready signal
coordinating the initiation of the device's synchronous read
operation with the start of an FPGA configuration sequence.
Optionally, READY_WAIT can be dynamically configured as
an output wait signal, indicating a wait condition during a
synchronous read operation.
Upon a power-on reset (POR) or RP-pin reset event, the
device drives READY_WAIT to V_IL until the device is ready to
initiate a synchronous read or receive a command. When the
device reaches an internal ready state from a reset condition,
READY_WAIT is released to a high-impedance state (an
external pull-up resistor to V_DDQ is required to externally pull
the READY_WAIT signal to a valid input High). The device
waits until the READY_WAIT input becomes a valid input
High before permitting a synchronous read or accepting a
command. Connecting the READY_WAIT to the FPGA
INIT_B pin in a wired-and circuit creates a handshake
coordinating the initiation of the device synchronous read
with the start of the FPGA configuration sequence.
When READY_WAIT is an input/open-drain ready signal, the
system can drive READY_WAIT to V_IL to reinitiate a
synchronous read operation. A valid address must be provided
to the device for a reinitiated synchronous read operation.
Optionally, READY_WAIT can be configured as an output
signaling a wait condition during a synchronous read
operation. The wait condition indicates a clock cycle during
which the output data is not valid. When configured as an
output wait signal, READY_WAIT is high impedance when
Chip Enable is at V_IH or Output Enable is at V_IH. Only when
configured as a wait signal, READY_WAIT can be configured
to be active during the wait cycle or one clock cycle in
advance, and the READY_WAIT polarity can be configured.
V_DD Supply Voltage
V_DD provides the power supply to the internal core of the
memory device and is the main power supply for all
operations (Read, Program and Erase).
V_DDQ Supply Voltage
V_DDQ provides the power supply to the I/O pins and enables
all outputs to be powered independently of V_DD.
V_PP Program Supply Voltage
V_PP is either a control input or a power supply pin, selected
by the voltage range applied to the pin.
If V_PP is kept in a low voltage range (0V to V_DDQ), V_PP is
seen as a control input. In this case a voltage lower than
V_PPLK gives absolute protection against program or erase,
while V_PP in the V_PP1 range enables these functions. V_PP is
only sampled at the beginning of a program or erase — a
change in its value after the operation starts does not have
any effect, and all program or erase operations continue.
If V_PP is in the range of V_PPH, the signal acts as a power
supply pin. In this condition V_PP must be stable until the
Program/Erase algorithm is completed.
V_SS Ground
V_SS Ground is the reference for the core supply and must
be connected to the system ground.
V_SSQ Ground
V_SSQ Ground is the reference for the input/output circuitry
driven by V_DDQ. V_SSQ must be connected to V_SS.
Note: Each device in a system should have V_DD, V_DDQ and V_PP
decoupled with a 0.1 μF ceramic capacitor close to the pin (high-
frequency, inherently low-inductance capacitors should be placed
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
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