DS617 Datasheet, PDF (51/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

X-Ref Target - Figure 29
R
Platform Flash XL High-Density Configuration and Storage Device
A22–A0
L
K⁽²⁾
E
G
High
W
VALID ADDRESS
T
AVKH
T_LLKH
T_ELKH
T_KHQV
T
ELQV
T
GLQV
T
GLQX
T_ELQX
T
GHTZ
DQ15–DQ0 ^Hi-Z
VALID
READY_WAIT^{(1,2) Hi-Z}
T
GLTV
T
KHTV
DS617_23_101608
Notes:
1. The READY_WAIT signal is configured to be active during wait state. READY_WAIT signal is active Low.
2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the
active edge. Here, the active edge is the rising one.
3. The number of clock pulses in the dashed area depends on the latency (default latency = 7). The first clock that occurs while L is Low, latches
the address.
Figure 29: Single Synchronous Read AC Waveforms, CR4 = 0
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
51