DS617 Datasheet, PDF (56/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Table 31: Write AC Characteristics, Chip Enable Controlled⁽¹⁾
Symbol
Alt
Parameter
T_AVAV
T_WC Address Valid to Next Address Valid
Min
T_AVEH
Address Valid to Chip Enable High
Min
T_AVLH
Address Valid to Latch Enable High
Min
T_DVEH T_DS Data Valid to Chip Enable High
Min
T_EHAX T_AH Chip Enable High to Address Transition
Min
T_EHDX T_DH Chip Enable High to Input Transition
Min
T_EHEL T_CPH Chip Enable High to Chip Enable Low
Min
T_EHGL
Chip Enable High to Output Enable Low
Min
T_EHWH T_CH Chip Enable High to Write Enable High
Min
T_ELKV
Chip Enable Low to Clock Valid
Min
T_ELEH T_CP Chip Enable Low to Chip Enable High
Min
T_ELLH
Chip Enable Low to Latch Enable High
Min
T_ELQV
Chip Enable Low to Output Valid
Min
T_GHEL
Output Enable High to Chip Enable Low
Min
T_LHAX
Latch Enable High to Address Transition
Min
T_LLLH
Latch Enable Pulse Width
Min
T_WHEL(2)
Write Enable High to Chip Enable Low
Min
T_WLEL T_CS Write Enable Low to Chip Enable Low
Min
T_EHVPL
Chip Enable High to V_PP Low
Min
T_EHWPL
Chip Enable High to Write Protect Low
Min
T_QVVPL
Output (Status Register) Valid to V_PP Low
Min
T_QVWPL
Output (Status Register) Valid to Write Protect Low Min
T_VPHEH T_VPS V_PP High to Chip Enable High
Min
T_WPHEH
Write Protect High to Chip Enable High
Min
Voltage Range
V_DDQ =
2.3V to 2.7V
V_DDQ =
3.0V to 3.6V
85
85
50
50
10
10
50
50
0
0
0
0
25
25
0
0
0
0
9
9
50
50
10
10
85
85
17
17
9
9
10
10
25
25
0
0
200
200
200
200
0
0
0
0
200
200
200
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Sampled only, not 100% tested.
2. T_WHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers
should take this timing into account and can insert a software No-Op instruction to delay the first read in the same bank after issuing any
command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command
is a Read Array operation in a different bank and no changes to the Configuration Register are issued, T_WHEL is 0 ns.
X-Ref Target - Figure 33
W,E,G,L
RP
V ,V
DD DDQ
T
T^PHWL
T ^PHEL
T^PHGL
PHLL
T_PLWL
T
T^PLEL
T^PLGL
PLLL
T _VDHPH
T
PLPH
Power-Up
Reset
Figure 33: Reset and Power-Up AC Waveforms
DS617_50_090108
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
56