DS617 Datasheet, PDF (49/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 27
DQ15–DQ0 ^Hi-Z
VALID
VALID
VALID
NOT VALID
VALID
A22–A0
L
K⁽⁴⁾
E
VALID ADDRESS
T
AVLH
T
LLLH
T_LLKH
T_AVKH
T_ELKH
T_KHAX
Note 1
G
High
W
T
GLQX
T_GLTV
T
KHQV
T
KHQX
T
EHQX
T_EHQZ
T_EHEL
T
GHQX
T_GHQZ
READY_WAIT ^Hi-Z
T
ELTV
Note 2
T
KHTV
T
KHTX
Note 2
Note 2
T
EHTZ
Address
Latch
X Latency
Valid Data Flow
Boundary
Crossing
Valid
Data
Standby
DS617_22_053008
Notes:
1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register.
2. The READY_WAIT signal can be configured to be active during wait state or one cycle before. READY_WAIT signal is active Low.
3. Address latched and data output on the rising clock edge.
4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one.
5. The minimum system clock period is T_KHQV plus the FPGA data setup time.
Figure 27: Synchronous Burst Read AC Waveforms, CR4 = 0
X-Ref Target - Figure 28
T_KHKL
T
KHKH
T
T
F
R
T_KLKH
Figure 28: Clock Input AC Waveform
DS617_25_032708
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
49