DS617 Datasheet, PDF (67/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Table 44: Bank and Erase Block Region 1 Information^(1,2)
Offset
Data
Description
(P+24)h = 12Eh
0Fh
Number of identical banks within Bank Region 1
(P+25)h = 12Fh
00h
(P+26)h = 130h
Number of program or erase operations allowed in Bank Region 1:
11h
Bits 0–3: Number of simultaneous program operations Bits
4–7: Number of simultaneous erase operations
(P+27)h = 131h
Number of program or erase operations allowed in other banks while a bank in same region is
programming
00h
Bits 0–3: Number of simultaneous program operations
Bits 4–7: Number of simultaneous erase operations
(P+28)h = 132h
Number of program or erase operations allowed in other banks while a bank in this region is
erasing
00h
Bits 0–3: Number of simultaneous program operations Bits
4–7: Number of simultaneous erase operations
(P+29)h = 133h
Types of erase block regions in Bank Region 1 n = number of erase block regions with
01h
contiguous same-sized erase blocks. Symmetrically blocked banks have one blocking
region⁽²⁾.
(P+2A)h = 134h
(P+2B)h = 135h
(P+2C)h = 136h
(P+2D)h = 137h
07h
00h
Bank Region 1 Erase Block Type 1 Information:
Bits 0–15: n+1 = number of identical-sized erase blocks
00h
Bits 16–31: n×256 = number of bytes in erase block region
02h
(P+2E)h = 138h
(P+2F)h = 139h
64h
Bank Region 1 (Erase Block Type 1)
00h
Minimum block erase cycles × 1000
(P+30)h = 13Ah
Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC
Bits 0–3: bits per cell in erase region
01h
Bit 4: reserved for “internal ECC used”
BIts 5–7: reserved
(P+31)h = 13Bh
Bank Region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities
Bit 0: Page-mode reads permitted
03h
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3–7: reserved
Bank Region 1 Erase Block Type 2 Information
Bits 0–15: n+1 = number of identical-sized erase blocks
Bits 16–31: n×256 = number of bytes in erase block region
Bank Region 1 (Erase Block Type 2)
Minimum block erase cycles × 1000
Bank Regions 1 (Erase Block Type 2): Bits per cell, internal ECC
–
–
Bits 0–3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5–7: reserved
Bank Region 1 (Erase Block Type 2): Page mode and Synchronous mode capabilities
Bit 0: Page-mode reads permitted
Bit 1: Synchronous reads permitted
Bit 2: Synchronous writes permitted
Bits 3–7: reserved
Notes:
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank Regions. There are two Bank Regions, see Table 35, page 61.
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
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