DS617 Datasheet, PDF (57/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Table 32: Reset and Power-Up AC Characteristics
Symbol
Parameter
T_PLWL
T_PLEL
T_PLGL
T_PLLL
Reset Low to:
Write Enable Low,
Chip Enable Low,
Output Enable Low,
Latch Enable Low
T_PHWL
T_PHEL
T_PHGL
T_PHLL
T_PLPH(1),(2)
T_VDHPH
Reset High to:
Write Enable Low
Chip Enable Low
Output Enable Low
Latch Enable Low
RP Pulse Width
Supply Voltages High to Reset High
Notes:
1. A device reset is possible but not guaranteed if T_PLPH < 50 ns.
2. Sampled only, not 100% tested.
X-Ref Target - Figure 34
W, G, L
High
Test Condition
During Program
During Erase
Other Conditions
–
–
–
Min
Unit
60
μs
60
μs
60
μs
60
μs
50
ns
0
μs
E _Low
V_DD, V_DDQ
T
VDHPT
T
PLPH
RP
READY_WAIT
T
RWRT
T
RWL
T_PHRWZ
T
RWLRWH
T_PLRWL
T_RWRT
T_RWRT
Power-Up
Reset
READY_WAIT
(pulse)
DS617_29_090108
Notes:
1. READY_WAIT requires an external pull-up resistor to V_DDQ sufficiently strong to ensure a clean Low-to-High transition within less than T_RWRT
when the READY_WAIT pin is released to a high-impedance state.
Figure 34: READY_WAIT AC Waveform
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
57