DS617 Datasheet, PDF (2/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

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X-Ref Target - Figure 1
Platform Flash XL High-Density Configuration and Storage Device
Platform Flash XL
READY_WAIT
FPGA Design
(.bit) File
Configuration
Synchronization
Handshake
Clock up to 50 MHz⁽¹⁾
Wide (16-bit) Datapath
Up to 800 Mb/s
FPGA
DS617_01_102709
Notes:
1. System considerations can lower the configuration clock frequency below the maximum clock frequency for the device. To determine the
maximum configuration clock frequency, check the minimum clock period (T_KHKH) for the chosen I/O voltage range (V_DDQ), the clock High-
to-output valid time (T_KHQV), and the FPGA SelectMAP setup time.
Figure 1: Platform Flash XL Delivers Reliable, High-Performance FPGA Configuration
Platform Flash XL support is integrated with the Xilinx
design and debug tool suite.The iMPACT application,
included with the ISE software, supports indirect, in-system
programming of Platform Flash XL via the IEEE Standard
1149.1 (JTAG) port on the FPGA for prototype programming
(Figure 3).
X-Ref Target - Figure 2
Platform Flash XL
Code
User Data
Design (.bit)
File, Rev. 1
Design (.bit)
File, Rev. 0
Control
Address
Data/Commands
FPGA
User Design
X-Ref Target - Figure 3
DS617_02_081209
Figure 2: Standard NOR Flash Interface for User
Access to Memory
Single Cable Connector for
Direct FPGA Configuration/Debug and
Indirect Platform Flash XL
Programming
Xilinx JTAG
Cable Connector
FPGA
For Programming
Platform Flash XL
Platform Flash XL
FPGA Design
(.bit) File
Control
Address
Data/Commands
Indirect,
In-System
Programming
Engine
For Programming
Platform Flash XL
DS617_03_081209
Figure 3: Indirect Programming Solution for Platform Flash XL
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
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