DS617 Datasheet, PDF (52/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 30
DQ15–DQ0 ^Hi-Z
VALID
VALID
VALID
VALID
A22–A0
L
K⁽⁴⁾
E
VALID ADDRESS
T_AVLH
T_LLLH
T_LLKH
T_AVKH
T_ELKH
T_KHAX
G
READY_WAIT^{(2,5) Hi-Z}
T
ELTV
Note 1
T
GLQX
T_GLQV
T_GLTV
T
KHQV
Note 3
T
GHQZ
T_GHTZ
T_EHQX
T_EHQZ
T_EHEL
T
GHQX
T_EHTZ
High
W
DS617_24_053008
Notes:
1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register.
2. The READY_ WAIT signal is configured to be active during wait state. READY_ WAIT signal is active Low.
3. The CLOCK signal can be held High or Low.
4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the
active edge. Here, the active edge is the rising one.
5. From the moment data is valid, soon after G becomes asserted, the READY_WAIT signal reverts its previous level.
Figure 30: Synchronous Burst Read Suspend AC Waveforms, CR4 = 0
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
52