DS617 Datasheet, PDF (50/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Table 29: Synchronous Read AC Characteristics^(1,2)
Symbol
Alt
Parameter
Voltage Range
V_DDQ =
2.3V to 2.7V
V_DDQ =
3.0V to 3.6V
Units
T_AVKH
T_AVCLKH Address Valid to Clock High
Min
9
T_ELKH
T_ELCLKH Chip Enable Low to Clock High
Min
9
T_ELTV(3)
Chip Enable Low to Wait Valid
Max
17
T_EHEL
Chip Enable pulse width
(subsequent synchronous reads)
Min
20
T_EHTZ(3)
Chip Enable High to Wait Hi-Z
Max
17
T_KHAX
T_CLKHAX Clock High to Address Transition
Min
10
T_KHQV(4)
T_KHTV(3)
Clock High to Output Valid
T_{CLKHQV Clock High to WAIT Valid}
Max
16
T_KHQX
T_KHTX(3)
Clock High to Output Transition
T_{CLKHQX Clock High to WAIT Transition}
Min
2
T_LLKH T_ADVLCLKH Latch Enable Low to Clock High
Min
9
T_KHKH(4)
T_CLK Clock Period (f = 54 MHz)⁽⁴⁾
Min
19
T_KHKL
T_KLKH
Clock High to Clock Low
Clock Low to Clock High
Min
6
T_F
Clock Fall or Rise Time
Max
2
T_R
9
ns
9
ns
17
ns
20
ns
17
ns
10
ns
16
ns
2
ns
9
ns
19
ns
6
ns
2
ns
Notes:
1. Sampled only, not 100% tested.
2. For other timings, refer to Table 28, page 50.
3. Parameter applies when READY_WAIT is configured (CR4) with the output WAIT function.
4. The minimum system clock period is T_KHQV + FPGA data-to-CCLK setup time. See the FPGA data sheet for FPGA setup time.
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
50