DS617 Datasheet, PDF (40/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 20
V_DD/V_DDQ
READY_WAIT
First Address Latching Sequence
G
High
RP
E _Low
L
K
A22–A0
T
GLKH
T_GLKL
Address not Valid
1
T_AVKH3
2
3
4
T_KH3AX
First Address
DQ15–DQ0
FFFFh (Sync + Dummy Cycle)
DS617_52_102308
Notes:
1. Only on power-on-reset, FALS is initiated by READY_WAIT rising (Low-to-High) edge or G falling (High-to-Low) edge, whichever occurs last.
After POR, FALS is initiated only by a READY_WAIT rising edge.
Figure 20: First Address Latching Sequence (FALS)
Clock is not Free Running and G Transitions High-to-Low after READY_WAIT Goes High
Table 19: FALS Sequence Timings When the Clock Is Not Free Running
Symbol
Parameter
Voltage Range
V_DDQ =
2.3V to 2.7V
V_DDQ =
3.0V to 3.6V
T_AVKH3 Address setup on third positive edge of clock
Min
9
9
T_KH3AX Address hold on third positive edge of clock
Min
9
9
T_RWHKL Clock Low after READY_WAIT High
Min
600
600
T_RWHKH Clock High after READY_WAIT High
Min
600
600
T_GLKL Clock Low after G Low
Min
600
600
T_GLKH Clock High after G Low
Min
600
600
Unit
ns
ns
ns
ns
ns
ns
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
40