DS617 Datasheet, PDF (58/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Table 33: Power-Up Timing Characteristics
Symbol
Parameter
T_RWL(1)
T_RWLRWH
T_RWRT(2)
T_PHRWZ
T_PLRWL
T_RST
T_VDDPOR
T_VDQHPOR
T_VHRWZ
READY_WAIT Low driven from the device
READY_WAIT pulse driven from the system
READY_WAIT rise time
Time from RP High to when device releases READY_WAIT to high-
impedance state
Reset Low to READY_WAIT Low
Time required to trigger a device reset when V_DD drops below the
maximum V_DDPD threshold
V_DD ramp rate
V_DDQ ramp rate
Time from V_DD/V_DDQ POR thresholds to when device releases
READY_WAIT to high-impedance state
V_DDQ =
2.3V to 2.7V
Min
Max
60
–
50
–
–
1
–
200
–
50
5
15
0.2
50
0.2
50
5
15
V_DDQ =
3.0V to 3.6V
Min
Max
60
–
50
–
–
1
–
200
–
50
5
15
0.2
50
0.2
50
5
15
Unit
μs
ns
μs
μs
ns
ms
ms
ms
ms
Notes:
1. Depends on the V_DD/V_DDQ operating conditions.
2. READY_WAIT requires an external pull-up resistor to V_DDQ sufficiently strong to ensure a clean Low-to-High transition within less than
T_RWRT when the READY_WAIT pin is released to a high-impedance state.
Ordering Information
X-Ref Target - Figure 35
Example: XCF128X FTG64 C
Device Type
Operating Range
Package Type
C = Industrial (TA = –40°C to +85°C)
FT64 = 64-ball, Fine-Pitch Thin Ball Grid Array
FTG64 = 64-ball, Fine-Pitch Thin Ball Grid Array, Pb-free
DS617_11_050808
Notes:
1. See the FT64/FTG64 package specifications at http://www.xilinx.com/support/documentation/package_specifications.htm.
Figure 35: Ordering Information
Valid Ordering Combinations
Table 34: Valid Ordering Combinations
XCF128XFTG64C
XCF128XFT64C
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
58