DS617 Datasheet, PDF(11/88 Page) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

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DS617 Datasheet, PDF (11/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

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Platform Flash XL High-Density Configuration and Storage Device

Bus Operations

There are six standard bus operations that control the

device: Bus Read, Bus Write, Address Latch, Output

Disable, Standby and Reset (Table 5).

Bus Read

Bus Read operations are used to output the contents of the

Memory Array, Electronic Signature, Status Register and

Common Flash Interface. Both Chip Enable and Output

Enable must be at VIL in order to perform a read operation.

The Chip Enable input should be used to enable the device.

Output Enable should be used to gate data onto the output.

The data read depends on the previous command written to

the memory (see âCommand Interface,â page 14).

Bus Write

Bus Write operations write commands to the memory or

latch Input Data to be programmed. A Bus Write operation

is initiated when Chip Enable and Write Enable are at VIL

with Output Enable at VIH. Commands, Input Data and

Addresses are latched on the rising edge of Write Enable or

Chip Enable, whichever occurs first. The addresses can be

latched prior to the write operation by toggling Latch Enable

(when Chip Enable is at VIL).

The Latch Enable signal can also be held at VIL by the

system, but then the system must guarantee that the

address lines remain stable for at least TWHAX.

Note: Typically glitches of less than 5 ns on Chip Enable or

Write Enable are ignored by the memory and do not affect Bus

Write operations.

Address Latch

Address latch operations input valid addresses. Both Chip

enable and Latch Enable must be at VIL during address

latch operations. Addresses are latched on the rising edge

of Latch Enable.

Output Disable

The outputs are held at high impedance when Output

Enable is at VIH.

Standby

Standby disables most of the internal circuitry allowing a

substantial reduction of the current consumption. The

memory is in standby when Chip Enable and Reset are at

VIH. Power consumption is reduced to the standby level

IDD3, and the outputs are set to high impedance

independently from Output Enable or Write Enable. If Chip

Enable switches to VIH during a program or erase operation,

the device enters Standby mode when finished with the

program or erase operation.

Reset

During Reset mode, the memory is deselected and the

outputs are high impedance. The memory is in Reset mode

when Reset is at VIL. Power consumption is reduced to the

Reset level independently from Chip Enable, Output Enable

or Write Enable. If Reset is pulled to VSS during a Program

or Erase, this operation is aborted and the memory content

is no longer valid.

Table 5: Bus Operations(1)

Operation

Bus Read

Bus Write

Address Latch

Output Disable

Standby

Reset

FALS

E G W L RP

VIL VIL VIH VIL(4) VIH

VIL VIH VIL VIL(4) VIH

VIL

X VIH VIL

VIH

VIL VIH VIH

VIH

VIH X X

VIH

VIL(6)

VIL VIL VIH VIH

VIH

READY_WAIT(2,3)

CR4 = 1

CR4 = 0

Hi-Z

VIL(7)

Hi-Z

DQ15-DQ0

Data output

Data input

Data output or Hi-Z(5)

Hi-Z

Data output

Notes:

1. X = Don't care.

2. If READY_WAIT is configured as an output wait signal (CR4 = 0), then the CR10 Configuration Register bit defines the signal polarity.

3. READY_WAIT is configured using the CR4 Configuration Register bit.

4. L can be tied to VIH if the valid address was previously latched.

5. Depends on G.

6. The Configuration Register reverts to its default value after a Low logic level (VIL) is detected on the RP pin.

7. READY_WAIT pin used as an output. READY_WAIT goes Low TPLRWL after RP goes Low.

DS617 (v3.0.1) January 07, 2010

www.xilinx.com

Product Specification

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