DS617 Datasheet, PDF (29/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 11
V_DD/V_DDQ
READY_WAIT
G
T
VHRWZ
T
RWRT
First Address Latching Sequence
Latency cycles (default = 7)
L
T_RWHKL
K
T_AVKH3
T_KH3AX
1
2
3
4
A22–A0 Address not Valid
DQ15–DQ0
Address
FFFFh (Sync + Dummy cycle)
T
KHQV
D0 D1 D2 D3 D4 D5
DS617_44_053008
Notes:
1. W is tied High.
2. Address is latched on the third rising edge of K when G and E are Low, and L and READY_WAIT are High.
3. READY_WAIT requires an external pull-up resistor to V_DDQ sufficiently strong to ensure a clean Low-to-High transition within less than T_RWRT
when the READY_WAIT pin is released to a high-impedance state.
Figure 11: Power-Up
X-Ref Target - Figure 12
V_DD/V_DDQ
READY_WAIT
T_VHRWZ
T_RWRT
G
L
T_AVRWH
K
K1 2 3 4
T_RWHAX
A22-A0
Valid Address
T_KHQV
DQ15-DQ0
FFFFh
D0 D1 D2 D3 D4 D5 D6 D7 D8
Latency Cycles
(default = 7)
DS617_45_101508
Notes:
1. It is recommended to use the shown timings in the case of a free-running clock.
2. W is tied High.
3. K1 is the first clock edge from which both the READY_WAIT and the Output Enable signals are asserted (READY_WAIT at V_IH and G at V_IL).
Figure 12: Power-Up (Free-Running Clock)
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
29