DS617 Datasheet, PDF (26/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

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Platform Flash XL High-Density Configuration and Storage Device
Wrap Burst Bit (CR3)
The Wrap Burst bit (CR3) is used to select between wrap
and no wrap. Synchronous burst reads can be confined
inside the 4, 8 or 16-word boundary (wrap) or overcome the
boundary (no wrap). When this bit is Low (set to ‘0’), the
burst read wraps. When it is High (set to ‘1’), the burst read
does not wrap.
Burst Length Bits (CR2-CR0)
The Burst Length bits are used to set the number of words
to be output during a Synchronous Burst Read operation as
result of a single address latch cycle. These bits can be set
for 4 words, 8 words, 16 words or continuous burst, where
all the words are read sequentially. In continuous burst
mode, the burst sequence can cross bank boundaries.
In continuous burst mode, or 4, 8 or 16 words no-wrap,
depending on the starting address, the device asserts the
WAIT signal to indicate that a delay is necessary before the
data is output.
If the starting address is shifted by 1, 2 or 3 positions from
the four-word boundary, WAIT is asserted for 1, 2 or 3 clock
cycles, respectively, when the burst sequence crosses the
first 16-word boundary, to indicate that the device needs an
internal delay to read the successive words in the array.
WAIT is asserted only once during a continuous burst
access. See also Table 14, page 29.
CR14 and CR5 are reserved for future use.
X-Ref Target - Figure 9
K
1st cycle
X-latency
2nd cycle
3rd cycle
4th cycle
E
L
A22–A0
T
DELAY
DQ15–DQ0
VALID ADDRESS
T
AVK_CPU
T_ACC
T
T
QVK_CPU
K
T_KQV
T_{QVK_CPU}
VALID DATA VALID DATA
Figure 9: X-Latency and Data Output Configuration Example
DS617_42_032508
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
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