DS617 Datasheet, PDF (32/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Read Modes
Read operations can be performed in two different ways
depending on the settings in the Configuration Register. If the
clock signal is ‘don’t care’ for the data output, the read
operation is asynchronous; if the data output is synchronized
with clock, the read operation is also synchronous.
The read mode and format of the data output are determined
by the Configuration Register (see "Program/Erase
Controller Status Bit (SR7)," page 23). All banks support both
asynchronous and synchronous read operations.
Asynchronous Read Mode
In Asynchronous Read operations, the clock signal is ‘don’t
care’. Depending on the last command issued, the device
outputs the memory array data corresponding to the latched
address, the status register value, common flash interface
value, or electronic signature.
Note: The Read Mode Select bit (CR15) in the Configuration
Register must be set to '1' for asynchronous read mode operations.
Asynchronous Read operations can be performed in two
different ways: Asynchronous Random Access Read and
Asynchronous Page Read. Only Asynchronous Page Read
takes full advantage of the internal page storage so different
timings are applied. In Asynchronous Read mode a page of
data is internally read and stored in a Page Buffer.
A page has a size of 4 words and is addressed by address
inputs A0 and A1. The first read operation within the page
has a longer access time (t_AVQV, Random Access Time),
subsequent reads within the same page have much shorter
access times (t_AVQV1, Page Access Time). If the page
changes then the normal, longer timings apply again.
The device features an Automatic Standby mode. During
Asynchronous Read operations, after a bus inactivity of
150 ns, the device automatically switches to the Automatic
Standby mode. In this mode, the power consumption is
reduced to the standby value and the outputs are still driven.
In Asynchronous Read mode, when the READY_WAIT
signal is configured for the Wait function (CR4 = ‘0’), it is
always deasserted.
See Table 28, page 50, Figure 25, page 48, and Figure 26,
page 49, for details.
Synchronous Burst Read Mode
In Synchronous Burst Read mode, the data is output in
bursts synchronized with the clock. It is possible to perform
burst reads across bank boundaries.
Synchronous Burst Read mode can only be used to read
the memory array. For other read operations, such as Read
Status Register, Read CFI, and Read Electronic Signature,
Single Synchronous Read or Asynchronous Random
Access Read must be used.
In Synchronous Burst Read mode, the flow of the data
output depends on parameters configured in the
Configuration Register.
A burst sequence starts at the first clock edge (rising or
falling depending on Valid Clock Edge bit CR6 in the
Configuration Register) after the falling edge of Latch
Enable or Chip Enable, whichever occurs last. Addresses
are internally incremented and data is output on each data
cycle after a delay which depends on the X latency bits
CR13-CR11 of the Configuration Register.
The number of words to be output during a Synchronous
Burst Read operation can be configured as 4 words, 8
words, 16 words or continuous (Burst Length bits CR2-
CR0). The data can be configured to remain valid for one or
two clock cycles (Data Output Configuration bit CR9).
The order of the data output can be modified through the Wrap
Burst bit in the Configuration Register. The burst sequence is
sequential and can be confined inside the 4, 8 or 16 word
boundary (Wrap) or overcome the boundary (No Wrap).
The READY_WAIT signal configured for the Wait function
(CR4 = ‘0’) can be asserted to indicate to the system that an
output delay occurs. This delay depends on the starting
address of the burst sequence and on the burst configuration.
READY_WAIT (with CR4 = ‘0’) is asserted during the X
latency, the WAIT state and at the end of a 4, 8 and 16-word
burst. The signal is only de-asserted when output data is
valid or when G is at V_IH. In Continuous Burst Read mode,
a WAIT state occurs when crossing the first 16-word
boundary. If the starting address is aligned to the Burst
Length (4, 8 or 16 words), the wrapped configuration has no
impact on the output sequence.
The WAIT signal can be configured to be active Low or
active High by setting CR10 in the Configuration Register.
See Table 29, page 52: Synchronous Read ac
characteristics, and Figure 27, page 51: Synchronous Burst
Read ac waveforms, CR4 = 0, for details.
Synchronous Burst Read Suspend
A Synchronous Burst Read operation can be suspended,
freeing the data bus for other higher priority devices. The
operation can be suspended during the initial access latency
time (before data is output) or after the device has output
data. When the Synchronous Burst Read operation is
suspended, internal array sensing continues and any
previously latched internal data is retained. A burst sequence
can be suspended and resumed as often as required as long
as the operating conditions of the device are met.
A Synchronous Burst Read operation is suspended when
Chip Enable (E) is Low and the current address is latched
(on a Latch Enable rising edge, or on a valid clock edge).
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
32