DS617 Datasheet, PDF (21/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Status Register
The Status Register provides information on the current or
previous program or erase operations. A Read Status
Register command is issued to read the contents of the
Status Register, refer to "Read Status Register Command,"
page 14 for more details. To output the contents, the Status
Register is latched and updated on the falling edge of the
Chip Enable or Output Enable signals and can be read until
Chip Enable or Output Enable returns to V_IH.
The Status Register can only be read using single
asynchronous or synchronous reads. Bus Read operations
from any address within the bank always read the Status
Register during program and erase operations if no Read
Array command is issued.
The various bits convey information about the status and
any errors of the operation. Bits SR7, SR6, SR2 and SR0
give information on the status of the device and are set and
reset by the device. Bits SR5, SR4, SR3 and SR1 give
information on errors and are set by the device but must be
reset by issuing a Clear Status Register command or a
hardware reset.
If an error bit is set to ‘1’, the Status Register should be
reset before issuing another command.
The bits in the Status Register are summarized in Table 11.
Table 11: Status Register Bits
Bit
Name
SR7
P/E.C. Status
Type
Status
SR6
Erase Suspend Status
Status
SR5
Erase/Blank Check
Status
Error
SR4
Program Status
Error
SR3
V_PP Status
Error
SR2
Program Suspend
Status
Status
SR1 Block Protection Status
Error
Bank Write Status
Status
SR0
Multiple Word Program
Status (Buffer Enhanced
Factory Program mode)
Status
Logic
Level⁽¹⁾
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
'1'
'0'
Definition
Ready
Busy
Erase suspended
Erase In progress or completed
Erase/blank check error
Erase/blank check success
Program error
Program success
V_PP invalid, abort
V_PP OK
Program suspended
Program In progress or completed
Program/erase on protected block, abort
No operation to protected block
SR7 = ‘1’
Not allowed
SR7 = ‘0’
Program or erase operation in a bank other
than the addressed bank
SR7 = ‘1’
No program or erase operation in the device
SR7 = ‘0’
Program or erase operation in addressed
bank
SR7 = ‘1’
Not allowed
SR7 = ‘0’
The device is NOT ready for the next Buffer
loading or is going to exit the BEFP mode
SR7 = ‘1’
The device has exited the BEFP mode
SR7 = ‘0’
The device is ready for the next Buffer
loading
Notes:
1. Logic level '1' is High, '0' is Low.
Program/Erase Controller Status Bit (SR7)
The Program/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive in any
bank. When this bit is Low (set to ‘0’), the Program/Erase
DS617 (v3.0.1) January 07, 2010
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Product Specification
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