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| DS617 Datasheet, PDF (31/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage | |||
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R
X-Ref Target - Figure 15
RP
READY_WAIT
T
PLPH
TPLRWL
TPHRWZ TRWRT
Platform Flash XL High-Density Configuration and Storage Device
G
High
L, W
K
Latency Default Cycles
A22âA0
DQ15âDQ0
Address not Valid
Valid
Address
FFFFh
X-Ref Target - Figure 16
RP
READY_WAIT
Figure 15: RP Pulse (Clock is not Free Running)
TPLPH
TPHRWZ
TRWRT
Low
G
L, W High
K
TPLRWL
TAVRWH
K1 2 3 4
TRWHAX
T
KHQV
D0 D1 D2 D3 D4 D5
Valid Data
DS617_48_101508
A22-A0
Valid Address
TKHQV
DQ15-DQ0
FFFFh
FFFFh
D0 D1 D2 D3 D4 D5 D6 D7 D8
Latency Cycles
(default = 7)
DS617_49_101608
Notes:
1. It is recommended to use the shown timings in the case of a free-running clock.
2. K1 is the first clock edge from which both the READY_WAIT and the Output Enable signals are asserted (READY_WAIT at VIH and G at VIL).
Figure 16: RP Pulse (Free Running Clock)
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
31
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