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| DS617 Datasheet, PDF (41/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage | |||
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R
X-Ref Target - Figure 21
VDD/VDDQ
READY_WAIT
T
GLRWH
G
High
RP
Platform Flash XL High-Density Configuration and Storage Device
T
RWHAX
E Low
L
K
TAVRWH
A22âA0
1
2
3
4
First Address
DQ15âDQ0
FFFFh (Sync + Dummy Cycle)
Figure 21: First Address Latching Sequence (FALS): Clock is Free Running
DS617_16_081309
Table 20: FALS Sequence Timings with Free-Running Clock
Symbol
Parameter
TAVRWH Address Valid before READY_WAIT High
Min
TGLRWH Output Enable Low before READY_WAIT High
Min
TRWHAX Address Hold time after READY_WAIT High
Min
Notes:
1. 4tK = Fourth rising edge of clock (K) after READY_WAIT goes High.
Voltage Range
VDDQ =
2.3V to 2.7V
200
200
4tK + 200(1)
VDDQ =
3.0V to 3.6V
200
200
4tK + 200(1)
Unit
μs
μs
μs
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
41
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