DS617 Datasheet, PDF (46/88 Pages) Xilinx, Inc – MultiBoot Bitstream, Design Revision Storage

R
Platform Flash XL High-Density Configuration and Storage Device
Table 27: DC Characteristics: Voltages
Symbol
Parameter
V_IL
V_IH
V_OL
V_OH
V_PP1
V_PPH
V_PPLK
V_DDPD
V_DDPOR
V_DQPOR
Input Low voltage
Input High voltage
Output Low voltage
Output High voltage
V_PP program voltage-logic
V_PP program voltage factory
Program or erase lockout
V_DD power-down threshold
V_DD power-on reset threshold
V_DDQ power-on reset threshold
X-Ref Target - Figure 25
A22–A0
VALID
Test condition
–
–
I_OL = 100 μA
I_OH = –100 μA
Program, Erase
Program, Erase
–
–
–
–
T
AVAV
L⁽²⁾
T_AVLH
T_LLLH
T
ELLH
T_AVQV
T_LHAX
T
LLQV
E
T
ELQV
T
ELQX
G
DQ15–DQ0 ^Hi-Z
T_GLQV
T_GLQX
Min
Typ
Max
Unit
0
–
0.4
V
V_DDQ –0.4
–
–
V_DDQ + 0.4 V
–
0.1
V
V_DDQ –0.1
–
–
V
V_DDQ –0.4
–
V_DDQ +0.4
V
8.5
9.0
9.5
V
–
–
0.4
V
–
–
1.5
V
–
–
1.6
V
–
–
1.6
V
VALID
T
AXQX
T
EHQZ
T
EHQX
VALID
T_GHQX
T_GHQZ
READY_WAIT^{(1) Hi-Z}
T
GLTV
T_ELTV
T_GHTZ
Notes:
1. Write Enable, W, is High, READY_WAIT is active Low.
2. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported.
Figure 25: Asynchronous Random Access Read AC Waveforms, CR4 = 0
T
EHTZ
DS617_20_101608
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
46