W83C553F Datasheet, PDF (80/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
PCI Arbiter Control Register (default = 80h)
Type:
Read/Write
Bit Description:
Bit 7:
Bit [6:5]:
Bits [4:3]:
GAT. Guaranteed Access Timing. If set to a 1b, this bit enables Function 0 Flush Request and
Flush Acknowledge operation on pins 6 and 7 (provided pin 13 is not pulled low after reset).
This bit defaults to a 1b.
Reserved.
Arbiter Timeout Timer Value [2:0]
Number of clocks to wait for FRAME# to asset after GNT# is asserted
00 ATO time out after 16 clocks
01 ATO time out after 4 clocks
10 ATO time out after 8 clocks
11 ATO time out after 32 clocks
Bit 2:
Bit 1:
Bit 0:
Arbiter Timeout Timer Enable.
CPU Park Enable. Otherwise the arbiter will park on the last master. 0=Enable.
Bus Lock Enable. If set to 1b, this bit converts a PCI Lock cycle to a bus lock. If this bit is 0b,
the PCI arbiter ignores the LOCK# signal on the PCI bus.
WINBOND SYSTEMS LABORATORY
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