W83C553F Datasheet, PDF (46/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
3.14.3
PCI Target Abort Timing
The Target Abort cycle of Figure 3-11 starts when the target asserts DEVSEL# for one clock, then de-asserts DEVSEL# and
asserts STOP#. A target can use this sequence to indicate it cannot service the data transfer, and does not want the
transaction retried. The W83C553F cannot assume any data transfers in the current transaction were successful. It
terminates the current transfer with the de-assertion of FRAME#, and IRDY#. Since data integrity is not guaranteed, the
W83C553F cannot recover from a target abort event. Any on-going IDE activity will be stopped immediately, and an
interrupt will be generated if enabled. Abort and Error bits in the DMA Status register will be set. The PCI Configuration
registers will not be cleared. The PCI Configuration Space Status Register's RTA bit will be set to indicate the W83C553F
has received a Target Abort.
Figure 3-11. Target Abort Timing
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