W83C553F Datasheet, PDF (23/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Pin Descriptions
Pin Name
IDEDRQA
IDEDAKA#
IDEDRQB
IDEDAKB#
DA[2:0]
DD[15:0]
IDECHRDY
IDEIRQB
IDEIRQA
Table 2-4 (continued). IDE Interface Bus Signals
Pin #
Input/
Output Description
97
Input
DMA Request A. This signal is the primary port DMA handshake
from the IDE device. When asserted, it indicates a data transfer is
requested.
94
Output DMA Acknowledge A. This is the primary port DMA handshake to
the IDE device. When asserted, it indicates a data transfer can be
executed.
96
Input
DMA Request B. This is the secondary port DMA handshake from
the IDE device. When asserted, it indicates a data transfer is
requested.
93
Output DMA Acknowledge B. This is the secondary port DMA handshake
to the IDE device. When asserted, it indicates a data transfer can be
executed.
88,90,89
Output IDE Drive Address.
98,101,103,
105,108,
110,112,
114,115,
113,111,
109,106,
104,102,
100
95
Input/
Output
IDE Drive Data. 16-bit bi-directional bus.
Input
IDE I/O Channel Ready. When IDECHRDY is negated, the current
cycle will be extended. This input is connected to the primary port,
and can also be connected to the secondary port.
91
Input
IDE IRQ B. Secondary port interrupt request.
92
Input
IDE IRQ A. Primary port interrupt request.
WINBOND SYSTEMS LABORATORY
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