W83C553F Datasheet, PDF (75/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
Additional Break Event Enable Register (default = 00h)
Function:
This power management register may only be used while the W83C553F is in x86 mode.
Type:
Read/Write
Bit Description:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Reserved.
PCI SERR#. SERR Detection Enable. When this bit is "1," SERR detection is enabled. Upon
detection, the PMU will de-assert PMACT#.
IRQ0CLR. IRQ0 Clear. To clear IRQ0, write a "1", followed by a "0", to this bit.
ISA IOCHK#. IOCHK Detection Enable. When this bit is "1," IOCHK detection is enabled.
Upon detection, the PMU will de-assert PMACT#.
PCI PERR#. PERR Detection Enable. When this bit is "1," PERR detection is enabled. Upon
detection, the PMU will de-assert PMACT#.
NMI. NMI Detection Enable. When this bit is "1," NMI detection is enabled. Upon detection,
the PMU will de-assert PMACT#.
Interrupt. INTR Detection Enable. When this bit is "1," INTR detection is enabled. Upon
detection, the PMU will de-assert PMACT#.
PMUMGEN. GLOBAL Enable of Break Events. When this bit is "1," GLOBAL break event
detection is enabled. Upon detection, the PMU will de-assert PMACT#.
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