W83C553F Datasheet, PDF (121/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
Programming Interface Register ( Default = 8Ah)
Function:
There are no PCI predefined configuration register sets released for this class of device but the PCI SIG has
generated two proposed interfaces which are both supported. The first interface defines native and legacy
IDE devices and is described in PCI Rev. 2.1 spec. The Programming Interface register will support both
the native and legacy modes. Also the PCI SIG group has proposed a programming interface for Bus
Master IDE controllers. This register set and protocol is fully supported as indicated by bit 7 of this register
being set.
Type: Read/Write
Bit Description:
Bit 7:
Bit [6:4]:
Bit 3:
Bit 2:
Bus Master. This bit is hardwired to logic 1 to indicate support of the IDE BUS MASTER
register set and protocol.
These bits are reserved and hardwired to logic 0.
P1PROG. Port 1 Programmable is hardwired to a 1b. This indicates that bit 2 of this register is
R/W.
If this bit is 1b, indicating in native mode, base address register (2 and 3) can be programmed.
If it is 0b, indicating legacy mode, they can not be programmed and default address will be
used.
Bit 1:
Bit 0:
P0PROG. Port 0 Programmable is hardwired to a 1b. This indicates that bit 0 of this register is
R/W.
If this bit is 1b, indicating in native mode, base address register (0 and 1) can be programmed.
If it is 0b, indicating legacy mode, they can not be programmed and default address will be
used.
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