W83C553F Datasheet, PDF (26/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Pin Descriptions
Table 2-5 (Continued). ISA Bus Signals
Pin Name
Pin #
Input/
Output Description
IOCHRDY
135
Input/
Output
I/O Channel Ready. This signal is used by ISA slaves to extend the
transfer cycle beyond the default ready timer expiration.
BALE
168
Output Bus Address Latch Enable. This signal indicates that a valid
address is on the bus.
AEN
136
Output Address Enable. AEN is asserted during DMA cycles to prevent
I/O devices from misinterpreting the cycle as a valid I/O cycle.
TC
166
Output Termination Count. This signal is asserted to indicate that a DMA
channel's word count has reached terminal count.
DRQ[7:5, 3:0]
DAK[2:0]
1,203,198,
191,190,
193,196
194,192,
195
Input
DMA Request. DMA service request from the DMA controllers.
Output
Encoded DMA Acknowledge. The channel number of the
arbitration winner is encoded in binary. An external decoder is
required to generate DACK[7:5, 3:0]#. The inactive value is 100b.
IRQ[15, 14, 12:9,
7:3]
186,188,
183,181,
179,127,
154,157,
159,161,
163
Input
Interrupt Request.
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