W83C553F Datasheet, PDF (59/159 Pages) Winbond – SYSTEM I/O CONTROLLER WITH PCI ARBITER

W83C553F
Electrical Specifications
Signaled Target Abort
Status Register (default = 0200h)
Type:
Read/Write
Bit Description:
Bit 15:
Bit 14:
Bit 13:
Bit 12:
Bit 11:
Bits [10:9]:
Bit 8:
Bit 7:
Bit 6:
Bit 5:
Bits [4:0]:
Detected Parity Error (DPE). This bit is read/write.
Signaled System Error (SSE).
Received Master Abort (RMA). This bit is read/write.
Received Target Abort (RTA). This bit is read/write.
Signaled Target Abort (STA). This bit is read/write.
DEVSEL# Timing (DVSLT). Medium speed. These read only bits are both set to "01".
Master Data Parity Error Detected (MDPE). This bit is read/write.
Fast Back-to-Back Capable (FB2BC). W83C553F does not decode fast back-to-back cycles
across different targets. This read only bit is set to "0".
UDF Supported (UDFS). W83C553F does not support user definable features. This read only
bit is set to "0".
66 MHz Capable (PCI66C). W83C553F does not support 66 MHz bus speed. This read only
bit is set to "0".
Reserved. This read only bit is set to "0".
WINBOND SYSTEMS LABORATORY
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